It has been a long time since equipments employing digital techniques had come to be put to practical use. In such an equipment, a D/A converter is used in a process in which a digital processing is performed on a digital quantity obtained as a result of a digitization of an analog quantity and thereafter another digital quantity representing the result of the digital processing is converted into another analog quantity. Heretofore, a D/A converter of what is called the resistance-ladder type, which is typified by an R-2R ladder D/A converter, has been used for such a purpose. Nowadays, integrated-circuit (IC) D/A converters have been developed with the intention of reducing costs. Increase in quantization number, however, results in rise of production costs of IC D/A converters for obtaining a desired conversion precision because of the fact that the conversion precision of an IC D/A converter depends on the accuracy of resistance of the internal circuit thereof. Recently, it has come to attempt to increase the conversion precision of a D/A converter by employing a PWM IC D/A circuit which can obtain a desired conversion precision independent of the accuracy of the resistance of the internal circuit thereof by utilizing a logic circuit thereof and employing PWM. However, with increase in conversion precision, the frequency of a fundamental clock input to the PWM D/A converter increases to the extent that no clocks supplied by a crystal oscillator for outputting a fundamental wave can have. Thus a frequency multiplier is employed therein as a countermeasure to such a problem.
However, lately, three kinds of equipments (namely, a compact-disk player (CD), a digital audio tape recorder (DAT) and a broadcasting-by-satellite (BS) tuner) respectively using different sampling frequencies have been put to practical use. As the result, a clock, the frequency of which is a specific multiple of the input sampling frequency, becomes necessary as a PCM clock. Further, it becomes necessary to change the frequency of a PWM clock according to the sampling frequency of an input signal, on which a D/A conversion should be performed. Furthermore, as described above, the frequency of a clock to be input to the PWM D/A converter becomes too high for the fundamental oscillation of a crystal oscillator to supply. Thus, a frequency multiplier employing a phase lock loop, another frequency multiplier utilizing what is called overtone oscillations and a frequency doubler utilizing an inductance or transformer (namely, a device for obtaining various frequencies, which are twice, triple or more the frequency of the fundamental oscillation, by utilizing parallel resonance achieved by means of an inductance and a capacity connected in parallel) have been proposed as means for obtaining higher clock frequencies. The frequency multiplier utilizing overtone oscillations and the frequency doubler, however, are unsuited for IC fabrication because they require inductive components. Consequently, the frequency multiplier employing a PLL is usually used. At that time, a spectrum of an unnecessary frequency component in case of performing a frequency division in a switching circuit, as well as a spectrum of another unnecessary frequency component occurring due to lead-lag filter characteristics of the frequency multiplier employing a PLL, is observed as illustrated in FIG. 1. Thus it turns out that the S/N of the PWM D/A converter is degraded due to the spectra of the unnecessary components. The results of a simulation of the manner of such degradation is described in an article entitled "Consideration on Clock Jitters in PWM D/A Converters", T. Kaneaki et al. (Matsushita Electric Industrial Co., Ltd. AV Research Laboratory), Kouen-Ronbun-Shu (in Japanese), The Acoustical Society of Japan, October 1988, pp. 411-412. It is described in this article as a conclusion of the simulation that "a clock jitter increases a noise level and further the noise level is proportional to the quantity of jitters". When an unnecessary spectrum is generated at a frequency, which is one nth the frequency of the fundamental wave of a clock to be input to a PWM D/A converter (incidentally, n is a given integer), as shown in FIG. 1 (incidentally, FIG. 1 illustrates a case where n is equal to 2), an output signal has waveforms of FIG. 2, which is represented with respect to time. Waveform (a) of FIG. 2 is a waveform diagram for showing a waveform of the output signal in case where only the fundamental wave of the clock for the PWM D/A converter is present. Waveform (b) of FIG. 2 is a waveform diagram for showing another waveform of the output signal in case where a wave (hereunder sometimes referred to as a one-half frequency-division wave), the frequency of which is one-half the frequency of the fundamental wave of the clock, is mixed into the fundamental wave of the clock for the PWM D/A converter. Namely, waveform (b) of FIG. 2 shows the output signal, which is represented with respect to time, in case where the signal having the spectra of FIG. 1, which is represented with respect to frequency, is input to the converter.
Then, if an output signal of the logic circuit of the converter is made to pass through an amplifier shown at a, of FIG. 3, which is of the type that feeds back an output signal of an inverter of the logic circuit of the converter to an input terminal of the inverter, the waveform of the output signal thereof becomes as illustrated in FIG. 1(b) or 1(c). Namely, the waveform of the output signal of the amplifier, which is output therefrom in case where only the fundamental wave (a) of FIG. 2 is input to the converter, becomes as illustrated at (b) in FIG. 3. Further, the waveform of the output signal of the amplifier, which is output therefrom in case where both of the fundamental wave of (b) in FIG. 3 and the one-half frequency division wave are input to the converter, becomes as illustrated at (c) in FIG. 3. Namely, in case of the waveform (c) of FIG. 3, jitters occur and as the result noises are increased as described in the foregoing article. Further, an example of the frequency multiplier utilizing a PLL is illustrated in FIG. 4. As shown in FIG. 4, an input signal V.sub.in is input from an input terminal 31 to a phase comparator 32. Moreover, an output of a frequency divider 35, the division ratio of which is (1/n), is also input to the phase comparator 32. Then, an output of the phase comparator 32 is input to a low-pass filter (LPF) 33. The oscillation frequency of a C-R voltage-controlled oscillator (VCO) 34 is controlled according to an output of the LPF 33. An output signal of this VCO 34 is issued from a terminal 36 thereof as a clock signal (f.sub.p).
Here, it is assumed that the input signal V.sub.in is represented by EQU V.sub.in =Asin(.omega..sub.in t+.theta.(t)) (1)
where A denotes the amplitude of the input signal; .omega..sub.in the angular frequency thereof; and .theta.(t) the phase thereof.
Moreover, it is supposed that an output signal of an frequency divider 35 is obtained by ##EQU1##
Generally, a sinusoidal output is not obtained as the output of the frequency divider 35. Thus a harmonic, the frequency of which is an integral multiple of that .omega..sub.in, is generated as the output thereof. Further, a multiplier is employed as the phase comparator 32. Therefore, an output V.sub.c thereof can be represented by EQU V.sub.c =V.sub.in .multidot.V.sub.out ( 3).
Then, substitution of the equations (1) and (2) into the equation (3) gives ##EQU2## Further, the equation (4) can be rewritten as follows by removing .SIGMA. from the second term on the right hand thereof: ##EQU3## Furthermore, the equation (5) can be rewritten as follows by expanding each term on the right hand thereof, which has the form of sin.times.cos: ##EQU4## Thus a harmonic, the angular frequency of which is an integral multiple of .omega..sub.in, is produced as an output of the phase comparator 32. Generally, the values of the amplitudes B.sub.j of the above described equations meet the following inequality: EQU B.sub.1 &lt;B.sub.2 &lt;B.sub.3 &lt; . . . . . . &lt;B.sub.j &lt; . . . .
Then, ordinary harmonic components are eliminated by the LPF 33 which is employed in the PLL. Incidentally, a lead-lag type LPF is employed as the LPF to ensure what is called a fast pull-in position characteristic of the PLL. The lead-lag type filter, however, has characteristics that the amplitude thereof does not converge on zero but becomes constant and in a high-frequency region. Thus a control signal including harmonics, the frequencies of which are integral multiples of .omega..sub.in, is input to the C-R VCO 34. As the result, unnecessary spectra are respectively generated at frequencies of f.sub.in .times.1, f.sub.in .times.2, f.sub.in .times.3 . . . . . . f.sub.in .times.j when an output of the C-R VCO 34, namely, a clock output therefrom is in a state in which the amplitude level thereof is largest at the frequency of f.sub.P =n.multidot.f.sub.in. Consequently, there is raised a problem that jitters are generated due to components, which have frequencies lower than f.sub.P, corresponding to these unnecessary spectra as described above (by referring to FIGS. 1 to 3) and thus the S/N of the PWM D/A is degraded.
The present invention is accomplished to resolve such a problem. It is, accordingly, an object of the present invention to provide a clock reproducing circuit for eliminating an unnecessary spectrum.